The present invention relates to the field of data communication. More specifically an embodiment of the present invention relates to the field of serially transmitting framing information bit-interleaved with data characters.
Bit interleaved framing has been used in data communication in the past. It is used in PDH (Plesiochronous Digital Hierarchy) in normal voice level telecommunication. Telephone companies used bit interleaving in their T1 and T3 modes of operation. In a T3 line, a transmitter inserts framing bits at fixed locations in the data stream; e.g. one every 171 bits according to a pre-determined sequence of bits. At the receive end, the receiving device looks at one bit in the data stream and waits 170 bits and looks at the same bit location in the data stream again and repeats the process for several times. Each examined bit is compared for a match with the pre-determined sequence of framing bits. From the framing bits, a frame boundary is determined and individual bytes are taken out of the data stream. The framing bits give the boundary of the data transmitted.
The telephone companies, however, abandoned this method of framing when high-speed transmission, e.g., in excess of 45 Mbits/second, was required. At data rates faster than T3, voice and data are transmitted with SONET protocols which use character-based framing. SONET protocols are used for data rates greater than 51 Mbits/second. In SONET protocols, a sequence of framing characters is used to mark the frame boundaries. At the receiving end, detection of the sequence of framing characters provides the frame boundary.
However, character-based framing has its disadvantages. One disadvantage being that character-framing demarcation leaves gaps in time between data information characters. Gaps between a group of data information characters are not tolerated in certain types of data transmission. For example, in Radio Frequency (RF) communication where constant direct modulation is required (e.g., I/Q modulation), modulation cannot be stopped for even a brief period of time. Gaps in modulation caused by the presence of framing characters in the modulation vector stream are not tolerated. Therefore, a need exists for a method of sending framing information, for a character-oriented data stream operated faster than T3 rates, in a form that avoids the generation of gaps in the delivered character stream caused by the framing information.
Wireless (radio-frequency) cellular telecommunication generally uses several transmitting antennas, with each transmitter generating a signal consisting of both in-phase and quadrature modulation components. These modulation components are generally delivered to the transmitter as 19-bit binary symbols which are used as inputs to digital-to-analog (D/A) converters. In one example these signals may be provided to each transmitter across a 19-bit wide parallel path, with said path consisting of 18 bits of data and a parity bit, with new symbols provided continuously at a 70-MHz rate. The data throughput required for this example interface exceeds 1 Gbit/second.
As shown in FIG. 1A, parallel interfaces have generally been used to provide high-speed communication of data. FIG. 1A depicts a conventional communication system 180 for transmitting 19-bit source data. This conventional system sends data across a parallel data bus along with a clock. One implementation uses a 19-bit parallel bus for each of the data paths along with a 70-MHz clock. These signals are routed on a backplane between the source card and a digital to analog (D/A) card. Each source card presents six of these 19-bit buses which results in a high signal density on the backplane and its associated connectors. The wire density on the backplane is especially high when eight of these source cards are required for transmission. This requires the partitioning of the system based on the limitations of the backpanel and its connectors. In addition, the signals on these buses must also be sent with their associated clock, while maintaining skew control between all signals and their associated clock.
In parallel transmission systems, multiple signals are required to carry data from encoder cards to transmitter cards. The transfer of data is done across the backplane, as described in the previous text, and the multiple signals required for such transfer of data consume significant backplane resources. Specifically, if the cellular telecommunication supports a wide array of present and legacy communications standards, requiring separate sets of links for each standard, it will be very difficult to accommodate the extra links due to the limited routing resources and congestion on the backpanel. Therefore, a need exists for data transmission in excess of 1 Gbit/second without gaps in the stream of data transferred and without the use of a parallel-bus backplane.
FIG. 1B illustrates an improved communication system 190. To improve the method, the parallel bus of FIG. 1A was replaced with a set of LVDS (Low Voltage Differential Signaling) based serial links. Standard LVDS devices can accept and communicate parallel buses of 24-bits in width including a clock across four differential signal paths. The data is sent on several separate serial data streams, each carrying a subset of the total number of bits, along with a separate signal for the clock. According to this improved method, data is only serialized and not scrambled or encoded.
Therefore, the data is sent on several separate data streams, each serializing a number of bits, along with a separate link for the clock.
A disadvantage associated with the previous methods is that the multiple signals that make each communication channel (parallel or multiple LVDS serial) have to be delay matched, i.e., they have to be measured to the same electrical length. This is due to the fact that at the receiving end, data recovery is relative to the clock time reference received on one of the LVDS signals. If any signal path is slightly longer than the other, the receiving end samples the bits at the wrong place. Therefore, a slight difference in length between these four differential pairs may disturb the integrity of the data information captured at the receiving end.
Another disadvantage associated with the conventional methods is that because the data is not encoded or scrambled, it must be carried through a DC-coupled interface. This requires that the transmitter and receiver be coupled to a common signal ground reference, and often to a common power supply. This lack of encoding or scrambling also maximizes the inter-symbol interference between bits on the serial links. If the transmission is to occur over a significant distance; e.g.,  greater than 10 m, the links will not operate. These conventional methods require several signals, are subject to increased inter-symbol interference and are limited to operation distances of less than 10 m.
Therefore, a need exists for a method to a) transfer character-oriented data at high speed and without gaps in the stream of data, b) decrease the number of signals needed to transfer said data on or across a backplane, and c) reduce the inter-symbol interference of the data being sent, d) while allowing operation distances greater than 10 m.
Accordingly, embodiments of the present invention concern a method, system, architecture, and circuitry for high-speed serial character-based data transmission using bit-interleaved framing, enabling the elimination of gaps in the stream of data characters during the transmission. Transmission of data characters over a serial link (e.g., a differential pair) reduces the number of signals on the backplane required to transmit this data relative to a parallel architecture. The use of a single link also eliminates any channel-to-channel signal skew requirements. This allows the maximum link length to be determined by the ability of the link receiver to resolve a signal, instead of the ability to maintain matched delays across multiple signals. Embodiments of the present invention allow data encoding and scrambling thereby reducing inter-symbol interference and allowing the serial link to be AC- or DC-coupled. Embodiments may also use optical transmission links, balanced or unbalanced transmission lines, or circuit board transmission-line constructs. In another embodiment, NRZI encoding allows the true and complement signals to be connected without regard to the active state.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description which is illustrated in the following text and associated figures.
A method and system are described for serially communicating a character-based data stream, using bit-interleaved framing information, from a transmitting device to a receiving device. In one embodiment, the present invention concerns a method and system for interleaving a single bit of a framing-bit sequence to each of the plurality of data characters to demark each of the data characters. The receiving device-captures and extracts the plurality of data characters serially transmitted by the transmitting device with bit-interleaved framing bits.
In another embodiment, the transmitting device serially transmits the data characters with bit-interleaved framing bits at an integer multiple of the rate at which they are input to the transmitting device without gaps between consecutive characters.
In yet another embodiment, a receiving device captures the serial bit stream generated by the transmitter, and automatically determines the character boundaries when a predefined number or pattern of framing bits is found in consecutive received characters. In this embodiment, the position of the framing-bits in the character stream is located and/or determined, and an offset location of the data characters is sent to a barrel shifter (multiplexer) which recaptures the data character and all following data characters.
More specifically, the present invention concerns a high-speed communications link with character-oriented distributed framing. The transmitting device receives a character-based data stream from a data source, said data stream consisting of a plurality of multi-bit data characters. Bit-interleaved framing adds one or more bits (that may be generated by a framing-bit generator) to each of the plurality of data characters, marking the boundary of each of the plurality of data characters. The transmitting device serially transmits the stream of multi-bit data characters at a transmission rate that is an integer multiple of the input character rate. The receiving device captures the stream of multi-bit data characters, which was serially transmitted by the transmitting device. The receiving device locates the frame marker pattern, interleaved between the data characters, and recovers the plurality of multi-bit data characters.
In one embodiment, the data characters of the data stream arrive at the transmitting device in parallel and are n-bits in length. A respective framing bit is added to each. The (n+1)-bit result is fed to a parallel scrambler and then to a NRZI encoder. A serializer then serializes the (n+1)-bit data and the serial result is then transmitted over a serial communication link at a high signaling rate. The framing bit added to each input character is part of a framing sequence which is a predetermined sequence or pattern. Advantageously, the transmitted character-based data stream (using bit-interleaved framing information) is continuous, e.g., it does not contain any gaps in the character data.
In one embodiment, the receiving device of the present invention captures the character-based data stream (containing bit-interleaved framing information) from the communication link and deserializes the data into a parallel format. The parallel data is then decoded (e.g., NRZI decoded) and then descrambled. The parallel output of the descrambler is fed to a plurality of pipeline registers which are coupled to a framing detection logic circuit. The pipeline registers can store more than n-bits of character and framing data.
The framing detection logic circuit of the present invention examines each bit of the received data for the predetermined framing pattern. In one embodiment, the detection logic contains a detection circuit and state machine for each bit position of the character (inclusive of framing bits) to perform the examination. Each instance of the detection circuit and state machine is used to track the status of pattern matches at one of the (n+1) possible bit locations. This pattern can be observed after a predetermined number of characters have been received. Once a pattern match is found by one or more of said state machines, a signal is sent to a second circuit that checks for the presence of a xe2x80x9cone-and-only-onexe2x80x9d pattern match to determine the bit location of the framing pattern.
Once the bit location of the framing pattern is known, it remains at the same bit location for all characters received thereafter. Therefore, the known location of the framing bit is presented to a barrel shifter to set the proper character boundaries of the data character which may be spread across the plurality of pipeline registers. In other words, the output of the match detection logic is used to update the barrel-shifter with the proper offset of the n-bit character (plus framing bit) within the data stream. The obtained characters are then output in parallel format. The comparator also drives an output parity control signal to indicate bad parity until framing is discovered.